The configuration shown in FIG. 6 is known as the semiconductor device used for the conventional charge protection device. As shown in the drawing, the resin package 101 is embedded with FET 102 (hereinafter, represented as charge FET 102) as a switch for charging control, FET 103 (hereinafter, represented as discharge FET 103) as a switch for discharging control, and a protection IC 104. The line indicated by the dotted line 105 is the peripheral line of the resin package 101, the configuration of one package is implemented thereby.
The drain electrode of the charge FET 102 is fixed on the die pad inner lead 107 of the lead frame 106 through the silver paste. Then the source electrode 108 and the gate electrode 109 of the charge FET 102 are electrically connected to the inner lead 107 of the lead frame 106 through the wire 110.
The discharge FET 103 and the protection IC 104 are also the same as the charge FET 102; they are fixed on the lead frame 106 and electrically connected to the inner lead 107 through the wire 110 (For example, referred to the patent reference 1).
Also, the configuration shown in FIG. 7 is known as the semiconductor device embedded with a plurality of the conventional power MOSFET. As shown in the drawing, two MOSFETs 121 and 122 are fixed on the upper surface of the mounting section 123 of the lead frame, and the mounting section 123 is derived to the outside as four drain terminals 125 from the side of the side surface of the package 124. In addition, the gate terminals 126 and 127 and the source terminals 128 and 129 separated from the mounting section 123 are formed at the lead frame, and are respectively derived to the outside from the side surface opposite to the side surface of the package 124 derived as the drain terminal 125.
The source electrode 130 of MOSFET 121 and the source terminal 128 are electrically connected with three bonding wire, the source electrode 132 of MOSFET 122 and the source terminal 129 are electrically connected with three bonding wires 133. As shown in the drawings, it is able to achieve large current through a plurality of the bonding wires 131 and 133 respectively for the source electrodes 130 and 132 (For example, referred to the patent reference 2).
Furthermore, the configuration shown in FIG. 8 is known as the semiconductor device embedded with the conventional MOSFET. As shown in the drawing, the main surface of the silicon chip 141 formed with the power MOSFET is formed with the source pad (source electrode) 142 and the gate pad (gate electrode) 143, and the drain pad (not shown in the drawing) is formed at the back surface. Next, the silicon chip 141 is bonded to the upper surface of the die pad part 144 through the Ag paste, four leads 145 for the drains connected with the die pad part 144 are derived to the outside from the side of one side surface of the resin package 146.
The source pad 142 of the silicon chip 141 and the lead 148 for source are electrically connected by the Al ribbon 147, thereby reduce the on-resistance value. Then three leads 148 for source is derived to the outside from the side of the side surface of the resin package 146 at opposite side of the side surface that the lead 145 is derived. The gate pad 143 of the silicon chip 141 and the lead frame are electrically connected through the Al wire 149, such that the lead 150 for gate is derived to the outside from the side of one side surface of the resin package 146 (For example, referred to the patent reference 3).